1. Field of the Invention
The present invention relates to a multi-chip stack package assembly, and particularly relates to a multi-chip stack package which has better signal transmission efficiency and requires lower fabrication costs.
2. Description of Related Art
Along with the ongoing development of electronic technology, new generations of electronic products with more complex and user-friendly functions are coming forth to replace old products. In addition, new electronic products are designed to be lighter, thinner, shorter, and smaller. Accordingly, various high-density semiconductor packages are developed in semiconductor package technology, such as multi-chip stack package.
FIG. 1 is a schematic cross-sectional view of a conventional multi-chip stack package. Referring to FIG. 1, a multi-chip stack package 100 comprises a wiring substrate 110, a plurality of chips each having a front side provided with an active surface thereon, such as a first chip 120 and a second chip 130 which is disposed between the wiring substrate 110 and the first chip 120, a plurality of first bonding wires 140, a plurality of second bonding wires 150, and a plurality of solder balls 160. Each of the first bonding pads 122 of the first chip 120 is electrically connected to a first conductive channel 112 of the wiring substrate 110 via one of the first bonding wires 140. Each of the second bonding pads 132 of the second chip 130 is electrically connected to a second conductive channel 114 of the wiring substrate 110 via one of the second bonding wires 150. The solder balls 160 are disposed on an under surface of the wiring substrate 110 to be away from a front side of the second chip 130. As shown in FIG. 1, the first chip 120 has a front side and an active surface formed on top of the front side, and the first bonding pad 122 is disposed at the right side of the multi-chip stack package 100. Hence, the first conductive channel 112 inside the wiring substrate 110 needs to be re-routed to electrically connect the first bonding pad 122 to the solder ball 160b at the left side of the multi-chip stack package 100. Correspondingly, the second bonding pad 132 is disposed at the left side of the multi-chip stack package 100. Consequently, the second conductive channel 114 inside the wiring substrate 110 needs to be re-routed to electrically connect the second bonding pad 132 to the solder ball 160a at the right side of the multi-chip stack package 100.
However, a length of each of the first bonding wires 140 is different from a length of each of the second bonding wires 150. As a consequence, the time required for transmitting a signal from the first bonding pad 122 of the first chip 120 and of the second chip 130 to the first conductive channel 112 is different. Hence, the problem of signal delay occurs during the operation of the multi-chip stack package 100. In addition, re-routing the first conductive channel 112 and the second conductive channel 114, as described above, also causes signal delay.
To solve this problem, a conventional technique is to fabricate a redistribution layer (not shown) on the chip. After a wafer (not shown) is fabricated, a plurality of contacts (not shown) is exposed on the areas to be divided into chips. However, the contacts may not be arranged according to the designer's requirement. Hence, the redistribution layer is formed on the areas so that the exposed bonding pads can be arranged as required and electrically connected to the contacts respectively through the circuits of the redistribution layer. After the redistribution layer is completed, the wafer is then divided to form the chips.
However, the width (between 5-10 micrometers) of the circuits of the redistribution layer is becoming smaller and smaller, and the material thereof generally comprises gold, which is expensive and has bad electrical conductivity. Thus, the conventional multi-chip stack package does not provide satisfactory signal transmission efficiency and fabrication cost of such package is high. Further, in the conventional technique, the redistribution layer is formed on all the areas to be divided into chips in the wafer. However, the designer may need the redistribution layer to be formed on only a portion of the areas. For the above reason, the conventional technique reduces the utilization of the wafer and cannot satisfy the user's requirements. In addition, the redistribution layer needs to be fabricated in a clean room, which also increases the fabrication costs of the conventional multi-chip stack package.